The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technique effectively used for a device having a self-reset signal bus enabling high-speed signal transmission.
Through investigation of known arts after achieving the present invention, (1) Japanese Unexamined Patent Publication No. Sho 61 (1986)-144788, (2) Japanese Unexamined Patent Publication No. Hei 5 (1993)-047180, and (3) “A 940 MHz Data-Rate 8 Mb CMOS SRAM (1999 IEEE International Solid State Circuits Conference) were reported. The publication (1) discloses a semiconductor memory device capable of performing operation of automatically precharging a data output line after completion of data output with reliability by generating a reading end confirmation clock after lapse of predetermined time since an output of a data output buffer was received. The publication (2) discloses a semiconductor memory device of comparing and determining amplification levels of complementary input signals supplied to an amplification circuit for amplifying a read signal having a small amplitude by a comparison control and, on the basis of the comparison and determination, generating equalize/precharge signals to automatically equalize/precharge an output signal of the amplification circuit. In the literature (3), a timing of resetting a read data bus by a self reset circuit constructed by a buffer circuit, a delay circuit, and a reset circuit is generated from an output of a read data bus signal.